The chosen candidate will be a Senior Verification Engineer dedicated to the Processing business and help drive Dolphin Design’s product development. As a member of a multi-disciplinary team, you will be expected to develop the best architecture of the product targeting very edge-IoT applications (sensor fusion, keyword spotting, object detection, image classification, …) including machine learning (ML) and Artificial Intelligence (AI) aspects. You will help drive insightful and critical verification decisions to reach performance and power target objectives for product such as CHAMELEON micro-controller, PANTHER DSP, and RAPTOR neural processing unit.
Verification engineers at Dolphin Design are given key responsibilities at the development stage of the product development pipeline, including early discussions with architects to assess product requirements, rapid feature development and deployment. Candidates for this role must have a strong and multi-disciplinary technical background and the ability to drive results across organizational boundaries.
The job is located within the Processing IPs product line in Singapore site (Pasir Ris). We aim at building a strong core team of 10 technical people during the first semester of 2022 in order to reach 20 people by the end of 2022.
YOUR MAIN MISSIONS
- Responsible for functional and power-aware verification
- Understand functional requirement and design specifications
- Work closely with the architect and designers to define and execute the verification strategy. It includes:
- The definition of the verification plan (coverage-driven methodology)
- The development and debugging of advanced uVM-based verification testbench
- The development of the coverage strategy and tests for parametrized IPs (SystemVerilog language)
- Functional, performances and power aware verification
- RTL debugging, non-regressions, verification closure
- Provide support to project team members (design activities teams) during project execution
- Contribute to the continuous improvement and maintenance of the verification methodology and flow.
- Continuous improvements following latest techniques, tools, and technologies.
- Provide internal support and guidance for design activities.
- Participate in project assessment, set-up and execution working closely with project managers and others team members
THIS POSITION IS FOR YOU:
- Bachelor's Degree w/ 8+ years or MS w/ 5+ years or PhD w/ 3+ years in Electrical Engineering, Computer Engineering, or Computer Science.
- 5+ years as a design/verification engineer, establishing state-of-the-art design.
- Proficient in UVM-based verification methodology and languages (SystemVerilog is a must)
- Expert in developing UVM-based verification infrastructure (e.g. testbenches, VIPs, scoreboards etc)
- Knowledge of AMBA protocols and AMBA VIPs.
- Knowledge of ARM and/or RISC-V core integration
- Experience with formal verification is a big plus
- Experience in UPF design is a big plus.
- Design and verification methodologies
- HDL coding (VHDL, Verilog, SystemVerilog)
- UPF standards: UPF2.0/2.1 and static checks methodologies for low power verification
- UVM-based testbench infrastructure, coverage-driven methodology
- Formal verification with QuestaFormal is a plus
- Lint, CDC methodology with Questa CDC is a plus
- Low-power SoC architecture, design and implementation flows for ultra-low-power consumption
- EDA tools from Cadence, Mentor and Synopsys covering all steps of the flow
- Scripting: Tcl, Shell, Perl, Python …
- Linux/Windows working environment
- Leadership skills
- Good verbal and written communication skills. (English is a must)
- Flexible, proactive and result/delivery oriented across organizational boundaries
- Excellent problem-solving skills.
- Ability to work as individual contributor as well as a team player
- Base + AWS + variable bonus
- Benefits: Term-life, Hospitalization, Outpatient General Practitioner, Outpatient Specialist
WHO ARE WE
We are a subsidiary of Soitec, and an innovative and fast-growing semiconductor company.
We are now opening our new dedicated Edge Computing and AI branch at the same facility in Singapore (Pasir Ris). Our vision is to enable the largest possible AIoT / EDGE IoT semiconductor community to deliver products with ultimate energy efficiency and performance. Our mantra is simple: "Consume less energy while increasing performance". This requires a combination of the "best of breed" in power management, triggering interfaces, audio chain, MCU subsystem architecture and AI HW gas pedal.