As part of our development, our Layout team is looking for a Layout Designer (M/F).

As part of the Advanced Power Management team specialised in the design of mixed-signal IPs (Adaptive Body-Bias Generator, Adaptive Voltage Scaling, Battery Chargers, 32-kHz oscillators, etc.), you will participate in the design of the IPs' layout in different technologies (Bulk, FDSOI, FinFET).

During the development phases you will take responsibility for the layout development of the IPs, including the follow-up of younger layouters and reporting to the project manager.

You will work with the schematic design team to express and understand the electrical constraints. You will then be responsible for the layout of analogue blocks. Your objective will be to design the layout while guaranteeing the electrical and technological quality in the smallest possible space.

YOUR MISSIONS

Understand and assimilate the drawing rules (DRM) and constraints related to Bulk, FDSOI, Finfet technologie.

Plan layout activities in collaboration with the project manager for the organisation of the work (cost and development time estimates, risk analysis)

Elaborate the floorplan and the circuit layout routing in a minimum of surface in conformity with the schematic view, the drawing rules and the electrical constraints of the product

Ensure all layout verifications (DRC/LVS/DFM...)

Ensure compliance with quality procedures and layout design reviews in collaboration with the schematic view

Ensure the coaching and mentoring of younger layouters

Generate back-end product supplies for delivery to our customers (GDSII, netlist, footprint, metal_gds, gds_socket, gds2_options, etc.)

Generate the back-end views of the delivery packages for the customer

Set up the delivery shelf

Propose and specify the evolution of production methods and tools

THIS POSITION IS FOR YOU!

You have at least 5 years experience in layout design of analog microelectronic circuits, and you are passionate about the job. This position requires autonomy, rigour, methodology, with leadership qualities to evolve in a multi-trade and multi-cultural team.

Skills required

Technical knowledge

• Technologies : Bulk, FDSOI from 65nm to 22nm. FinFET is a plus
• Layout realisation: Virtuoso (Cadence)
• Layout verification: Calibre
• Environment/Script : UNIX/Linux, Skill (Cadence)

Know-how

• Analyse and understand an electronic diagram to transcribe it into a layout
• Use of CAD and DRC/LVS verification software
• Interest in programming and improving methods would be a plus

Soft skills

• Rigorous and demanding work quality
• Adaptability to changes
• Ability to communicate and make proposals

Salary package: Metallurgy agreement, executive status, 8 compensation time off, Time Savings Account, profit-sharing, payment for 60% of public transport costs, 0.25ct/km bicycle mileage allowance, luncheon vouchers

Partial remote working possible.